1. Field of Invention
The present invention relates generally to a semiconductor chip having an under bump metallurgy (“UBM”) structure and a plurality of pattern metallization layers, and more particularly, to a bumped semiconductor chip having low metallization series resistance and methods of fabricating the same.
2. Brief Description of the Prior Art
Semiconductor chip packages having an under bump metallurgy (“UBM”) structure and a plurality of pattern metallization layers are well known in the art.
FIG. 1A-C: Prior Art
FIG. 1A illustrates a cross-sectional view of a prior art semiconductor chip 100 having a silicon substrate 102, a metal interconnect structure 104 comprising three aluminum layers, M1, M2 and M3, a passivation layer 115 having a plurality of openings 103, a bump passivation layer 120 ((typically of polyimide or benzocyclobutene) having a plurality of openings 108, a UBM structure 110 and a conductive bump 105, such as a solder “ball” bump or pillar bump.
The metal interconnect structure 104 is formed on top of the substrate 102. The passivation layer 115 (typically of silicon nitride or silicon dioxide) includes a plurality of openings 103 to expose portions of the top layer of the metal interconnect structure 104. In the embodiment shown, layer M1 contacts the substrate 102. Layer M3 contacts the UBM structure 110 via the opening 103 in the passivation layer 115. Layer M2 contacts layers M1 and M3 through a plurality of vias 130.
The UBM structure 110 is formed on each of the plurality of openings 103. Conventional UBM structures are approximately 2-5 μm thick and comprise two or three layers of conductive metals. As shown in FIG. 1C, in a 3-layer UBM structure, a bottom layer of a adhesive metal, such as aluminum, that is approximately 0.15 μm thick provides adhesion to the top aluminum layer. Then, a middle layer of a barrier metal, such as nickel/vanadium, that is approximately 0.15 μm thick is deposited over the bottom layer to serve as a barrier to prevent metal migration between the top and bottom layers. Finally, a top layer of a conductive solderable metal, such as copper or gold, that is approximately 1-5 μm thick is deposited over the middle layer to allow the solder bump 105 to be successfully bonded to the UBM structure 110.
In a two-layer UBM structure, a bottom layer of an adhesive metal, such as titanium or chromium, that is approximately 0.15 μm thick provides adhesion to the top aluminum layer. Then, a top layer of a conductive solderable metal, such as copper or gold, that is approximately 1-5 μm thick is deposited over the bottom layer to allow the solder bump 105 to be successfully bonded to the UBM structure 110.
The bump passivation layer 120 includes a plurality of openings 108 to expose the UBM structure 110. Finally, the solder bump 105 is formed on the exposed UBM structure 110 such that the largest linear dimension of the UBM structure 110 is smaller than the diameter of the solder bump 105.
FIG. 1B depicts a top view of the prior art semiconductor chip 100. Dotted line 106 indicates the circumference of the solder ball 105. Dotted line 107 indicates the portion of the UBM structure 110 that is partially covered by the bump passivation layer 120.
A bumped semiconductor chip is generally fabricated as follows: first, a semiconductor chip is prepared having aluminum layers (e.g., M1, M2 and M3) on the surface of the chip. Next, a passivation layer is applied over the surface of the chip, portions of which is selectively removed to create one or more openings to expose the top aluminum layer. Next, a UBM structure is formed on each of the exposed aluminum layer openings using conventional sputtering, plating and patterning processes. Next, a bump passivation layer is applied over the layered surface of the chip, portions of which is selectively removed to create one or more openings to expose the UBM structure. Finally, a solder bump or pillar is formed on each of the exposed UBM structures using conventional processes.
It should be apparent to those skilled in the art that the indicated materials and dimensions for the UBM structure are illustrative only and not limiting, having been presented by way of example—other metals and thicknesses may be used. Typically, the selection of materials and dimensions are predetermined by a particular manufacturer's process and usually can only be changed in a limited fashion, for example, specifying better conductivity, depending on the manufacturing process. Further details of prior art UBM processes can be found in, for example, U.S. Pat. Nos. 6,787,903 and 5,904,859.
When electrical current flows within the chip 100, each layer, M1, M2 and M3, imparts an electrical resistance and contributes to the overall electrical series resistance of a device using the chip. The added series resistance can degrade the performance of the device. To minimize the series resistance, present techniques increase the thickness of the metal layers or use a material with better conductivity/lower resistance. However, using thicker metal layers require longer processing time for deposition and etch, which in turn increases manufacturing costs. In addition, substituting metals with those having better conductivity/lower resistance, such as the standard aluminum with copper or gold, also increases processing complexity and cost because the use of copper or gold typically requires expensive specialized and/or dedicated equipment.